In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional sig...

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve high-throughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Conven...

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve highthroughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Convent...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

With the explosive growth in portable applications, power efficient computing in a Digital Signal Processor (DSP) is becoming a significant and challenging area of research. Clock-less or asynchronous timing is applied to eliminate clock generation, buffering and distribution at the system level. This paper presents the energy efficient functional unit for an asynchronous DSP implemented on fou...

Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than th...

Arithmetic functions are the most used operations in VLSI circuits. So the design of adders with high reliability and speed operation are of major concern in such circuits. This paper presents a methodology for designing totally self-checking Arithmetic adders for VLSI circuits and FPGA implementation using Verilog HDL. It detects the presence of all single stuck-at faults on-line that may occu...

If a CSP instance has no solution, it contains a smaller unsolvable subproblem that makes unsolvable the whole problem. When solving such instance, instead of just returning the “no solution” message, it is of interest to return an unsolvable subproblem. The detection of such unsolvable subproblems has many applications: failure explanation, error diagnosis, planning, intelligent backtracking, ...