Most approaches to the ramiication problem are based on the principle of minimization of change. It turns out, however, that this principle can not be applied uniformly, and many modern approaches use a clas-siication of the uents whereby change is only minimized in some of the uents. The present article reviews these approaches and their underlying motivations. It also presents a uniied formal...

For estimating delay parameters appearing in the CDMA (Code Division Multiple Access) model, several authors have proposed subspace-based solutions. Unfortunately, these methods , for example the eigenvector-based multiple signal clas-siication (MUSIC) method may yield poor results in noisy conditions. In this paper, we introduce subspace type delay estimation algorithms which are more eecient ...

functions of fundamental building blocks enables designers to optimize costs and propagation delays of the larger units built from them. A fundamental building block of an arithmetic logic unit (ALU) is the binary adder. In this article, we examine the implementation of fixed-point adders on Xilinx 4000 series FPGA chips and cost and delay functions of various addition algorithms. On the basis ...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

A Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latency and power consumption. In conventional methods, 10T XNOR s...

Recent advances in mobile computing and multimedia applications demand high-performance and lowpower VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a program...