A thorough understanding of the circadian clock requires qualitative evaluation of circadian clock gene expression. Thus far, no simple and effective method for detecting human clock gene expression has become available. This limitation has greatly hampered our understanding of human circadian rhythm. Here we report a convenient, reliable, and less invasive method for detecting human clock gene...

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing ...

The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of -23 dB is achievable at the input of the frequency divider within the clock receiver block. Introd...

We study the monitoring and fault-diagnosis problems for dense-time real-time systems, where observers (monitors and diagnosers) have access to digital rather than analog clocks. Analog clocks are infinitely-precise, thus, not implementable. We show how, given a specification modeled as a timed automaton and a timed automaton model of the digital clock, a sound and optimal (i.e., as precise as ...

Low power and robust circuitry are permanent hotspots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence ...

Clock distribution networks synchronize the flow of data in digital systems, and the features of the clock signal affect system performance and reliability. The great advances in integration levels and speed requirements in actual digital systems lead to enormous complexity in synchronization. Differences in delay of clock signals along clock paths, due to different lengths or active elements s...

Endogenous 24-hour rhythms are generated by circadian clocks located in most tissues. The molecular clock mechanism is based on feedback loops involving clock genes and their protein products. Post-translational modifications, including ubiquitination, are important for regulating the clock feedback mechanism. Previous work has focused on the role of ubiquitin ligases in the clock mechanism. He...

In this paper, we present an automatic clock tree design (ACTD) system for high speed VLSI designs. The ACTD is designed to extend the capabilities of the existing computer aided design tools and provides a convenient environment to CAD users. We have developed new theoretical analyses and heuristics. Specifically, the following issues are considered: (i) a planar clock routing, (ii) a solution...

Circadian clock is implicated in the regulation of aging. The transcription factor CLOCK, a core component of the circadian system, operates in complex with another circadian clock protein BMAL1. Recently it was demonstrated that BMAL1 deficiency results in premature aging in mice. Here we investigate the aging of mice deficient for CLOCK protein. Deficiency of the CLOCK protein significantly a...

This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. The clock tree topology is constructed based on the locations ...