Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface n...

Domino logic is a CMOS-based evolution of the dynamic logic techniques. It allows a rail-to-rail logic swing. It was developed to speed up circuits. In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatorial logic circuits, particularly those implemented in MOS technology. This work is oriented towards implementing the domino logic circuits...

Future technologies required nano-scale CMOS memory to be operating in low power consumption. The minimum operating voltage of the nano-scale CMOS played as a main factor to reduce the power consumption. Consequently, there are some limitations and obstacles to achieve the objective for several design, material and novel structural solutions, which are promising and reliable. In this research, ...

Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substit...

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation dela...

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic lo...

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interc...

A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurr...

In this paper we present novel ultra-low-voltage and high-speed CMOS NAND and NOR gates. For supply voltages below 500mV the delay for an ultra-low-voltage NAND2 gate is approximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch are much lesser than for conventional CMOS. Differential domino gates for AND2/NAND2 and OR2/NOR2 operation are presented. Ul...

Our present research endeavor focuses on the factors of hybrid single electron transistor (SET)-CMOS based static random access memory (SRAM). Ultra small low power dissipated SET is combined with high gain and high current drivable CMOS and the write operation of the memory cell is briefly analyzed. This work is a comparative work of power consumption between conventional CMOS based SRAM and h...