 Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-ErrorRate (BER). This paper describes an analog approach which applies fully differential current steering technique throughout the whole PLL sy...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

Recently deep submicron and SiGe (silicongermanium) bipolar CMOS technologies have enhanced the performance of Si-based radio frequency (RF) integrated circuits up to microwave frequencies. The integration of RF MEMS components, such as inductors and capacitors, could further improve the performance of key RF circuit blocks such as voltage controlled oscillators (VCO), low-noise amplifiers, fil...

CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry in VLSI dissipates less power when static, and is denser than other implementations having the same functionality. As this advantage has grown and become more important, CMOS processes and variants for VLSI have come to ...

A novel CMOS tunable transconductor is presented. The circuit operates in classAB hence featuring power efficiency. The internal feedback employed and the use of a linearized triode transistor for voltage-to-current conversion allows achieving high linearity. Rail-to-rail input range is obtained by using floatinggate transistors. Measurement results for a test chip prototype in a 0.5μm standard...

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SD...

Compressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well-established...

This paper presents the design and simulation of a 5GHz monolithic low-noise amplifier integrated with an active Balun. Intended to WLAN applications, the fully integrated circuit was implemented in a 0.18μm CMOS technology. The simulations, optimized to noise performance, gain and minimum differential phase and magnitude error, were performed with BSIM3 model. Circuit simulations present 23dB ...

We describe the design of an embedded 128-Kb Silicon-OnInsulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presen...

A 5Gb/s optical receiver front-end for optical interconnection is presented in this paper. A transimpedance amplifier (TIA), limiting amplifiers (LA), output buffer and a bias circuit are integrated in deep Nwell 0.18 m CMOS technology. As the input current amplitude is 30 A, the differential output voltage is achieved to be 124 mV. The linear gain is 78.8dB and consumes 200mW under 1.8V supply...