Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS Logic style gives best results over CMOS only and PTL o...

In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type o...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other exis...

In recent years, high-speed communication systems beyond 10Gb/s have been realized in CMOS technology. A 40Gb/s transmitter including the MUX has been developed in 0.13μm CMOS [1], and a 40Gb/s MUX/DEMUX in 90nm CMOS has been reported [2]. These circuits extend the bandwidth with inductive peaking for 40Gb/s operation. They use supply voltages that exceed the logic supplies used in these techno...

There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per clock cycle. Unfortunately, this assumption usually does not hold true in practice. In this article, we show that glitches occurring in circuits of masked gates make these circuits susceptible to classical first-order DPA...

This paper proposes a new quasi adiabatic logic family that uses two complementary pulsed supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) has switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. We have done a SPICE simulation on the chain of four 2PASCL inv...

An eecient technique to reduce the switching activity in a technology mapped CMOS combi-national circuit based on local logic transformations is presented. The transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and eecient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are ...

The input conductance of CMOS and many other integrated circuit technologies is determined mainly by the electrical properties of on-chip electrostatic discharge protection devices. Generally, they are designed to have diode-like characteristics to shunt potentially harmful static charge away from thin gate-oxide insulators. These nonlinear junctions may also rectify radio-frequency signals cou...

In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the transistor size in each stage power and delay can be minimized. This paper presents the analysis of full adders having efficient par...