The Spatially Modulated Light CMOS detector (SML CMOS detector) has taken away the conventional speed limit linked with photodetectors implemented in standard CMOS technology [1-3]. High-speed light detectors can be integrated with the CMOS receiver circuitry on the same silicon wafer without the usage of hybrid technology nor additional process steps. This indicates that the SML-detector will ...

wileyonlinelibrary.com recent rich advancements in strain engineering, [ 2 ] metal gate stack with high-k dielectrics, [ 3 ] and transistor architecture, [ 4 ] up to the development of Si FinFET devices adopted in current CMOS technology. It is expected that downscaling of Si-based technology will eventually reach its physical limits below 10 nm technology node, a bottleneck that research now t...

This paper presents a design of an UWB downconversion integrated CMOS resistive ring mixer with Linear Voltage Regulator (LVR), to supply required biasing voltages for the mixer section. The designed mixer circuit has been optimized for using in heart rate extraction system with microwave Doppler radar at 2.4GHz frequency. This mixer needs 2 DC bias voltages equal to 0.5 and 1 volts for its bes...

Quantum-dot cellular automaton (QCA) is a novel nanotechnology with a very different computational method in compared with CMOS, whereas placement of electrons in cells indicates digital information. This nanotechnology with specifications such as fast speed, high parallel processing, small area, low power consumption and higher switching frequency becomes a promising candidate for CMOS tec...

In this paper, an imaging chip for acquiring range information using by 0.35 μm CMOS technology and 5V power supply has been described. The system can extract range information without any mechanical movement and all the signal processing is done on the chip. All of the image sensors and mixed-signal processors are integrated in the chip. The design range is 1.5m-10m with 18 scales.

Since the last few decades the siliconbased technology has escalated remarkably. The reason behind the exceptional advancement of the CMOS devices is acknowledged due to its potential of being scaled down to increasingly compact sizes. However, the excessive scaling of CMOS devices to the Nano ranges have resulted in several non-idealities affecting the I/V characteristics and increased short c...

Over the past 50 years of the semiconductor industry, the size of MOSFETs has been scaled down obeying the Moore’s law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. However, as CMOS technology approaches nanoscale region, researchers face with critical technology barrier known as short channel effect. While the gate voltage fully controls the cha...

In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compati...

A new CMOS-based image sensor that is intrinsically compatible with onchip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 pm p-well CMOS process, and consists of a 128 x 128 array of 40 pm x 40 pm pixels. The CMOS image sensor technology ena...