A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146μW at 1.5V supply.

This paper presents the experimental evaluation of a fully-differential offset-compensated voltage comparator designed for use in multilevel (ML) Flash memory sensing. The comparator is made up by an input buffering stage followed by a gain stage that performs a regenerative action. The circuit has been integrated in a 0.13-μm triple-well Flash CMOS process. The experimental evaluation showed a...

A measurement System for detecting dark currents, generated by the TESLA cavities is proposed. It is based on the cryogenic current comparator principle and senses dark currents in the nA range. Design issues and the application for the CHECHIA cavity test stand are discussed.

Dynamic latched comparators are most used in analog-to-digital converters. In this paper expressions for the calculation of the offset voltage for two most used topologies are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of these comparators by analyzing the influence of each transistor pair individua...

Dynamic comparators are used in high speed analog to digital converters. In this paper low voltage, low power dynamic comparators are designed in 130 nm technology and the analysis of the power consumption and delay will be presented. Based on the presented analysis, a new dynamic comparator is proposed. By using power gating technique and adding few transistors, the positive feedback during th...

An ultrahigh-speed multiple-threshold comparator that consists of resonant-tunneling diodes (RTDs) and heterojunction FETs has been investigated. A novel multiple-threshold operation is obtained by detecting a switching sequence in a series-connected RTD circuit. SPICE simulation reveals that the present comparator operates at a clock frequency as high as 10 GHz. One FET at the input is enough ...

A CMOS rail-to-rail comparator operating at low-voltage supply by using a conventional fabrication process is proposed. Based on the comparator, an analog rank-order extractor with winner-take-all capability is presented. An experimental chip was fabricated using 0.5 m CMOS technology. Measured results at 1–V supply voltage show a comparator response time of 4 s for 10-mV precision and that the...

A novel universal QCA gate is introduced and called a boundary comparator. This gate implements a Boolean function in its boundary form, as a superposition of elementary boundary functions or as threshold functions having weights equal to integer powers of 2. An array of the boundary comparators is called Comparator based Programmable Array (CPA) and forms a homogeneous regular structure progra...

This paper describes a comparator that uses a gain stage as a preamplifier in the preamplification mode and as a latch in the latch mode. This method effectively reduces the power consumption of the comparator. Using a 1.2um CMOS process and applying offset cancellation to all of the circuit, an offset of less than 100uV at comparison rates up to 6MHz, with only a 130uW power dissipation and 3V...

Dynamic comparators are used in high speed analog to digital converters. In this paper low voltage, low power dynamic comparators are designed in 130 nm technology and the analysis of the power consumption and delay will be presented. Based on the presented analysis, a new dynamic comparator is proposed. By using power gating technique and adding few transistors, the positive feedback during th...