Active learning of register automata infers extended finite state machines (EFSMs) with registers for storing values from a possibly infinite domain, and transition guards that compare data parameters to registers. In this paper, we present RALib, an extension to the LearnLib framework for automata learning. RALib provides an extensible implementation of active learning of register automata, to...

In this paper, we present several techniques for modeling and formal verification of the Fairisle asynchronous transfer mode (ATM) switch fabric using multiway decision graphs (MDG’s). MDG’s represent a new class of decision graphs which subsumes Bryant’s reduced ordered binary decision diagrams (ROBDD’s) while accommodating abstract sorts and uninterpreted function symbols. The ATM device we i...

This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, w...

Higher microprocessor frequencies accentuate the performance cost of memory accesses. This paper presents novel, non-speculative techniques that partially hide the increasing load-to-use latency, by allowing the early issue of load instructions. Early load address resolution relies on register tracking to safely compute the address of memory references in the frontend part of the processor pipe...

Genetic algorithms have proven to be a viable solution to the NP-complete problem of test vector generation. However, the parameters used to control GA-based ATPG can greatly affect test set size, fault coverage, and CPU execution time. Knowing how a given set of parameters will affect each of these factors a priori allows for more efficient testing procedures. Over 1 million ATPG experiments w...

CPU port contention has been used in the last years as a stateless side channel to perform side-channel attacks and transient execution attacks. One drawback of this is that it heavily relies on simultaneous multi-threading, which can be absent from some CPUs or simply disabled by OS. In paper, we present sequential contention, does not require SMT. It exploits sub-optimal scheduling ports for ...

We describe two abstractions that show how Lamport’s Paxos and Castro and Liskov’s PBFT are essentially the same consensus protocol, but for different failure models. The first abstraction is a regular register that captures how processes in both protocols propose and decide values. The second abstraction is tokens that capture how these protocols guarantee agreement despite partial failures. T...