In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, but has significant area overhead. This paper explores the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the LUT inputs. We have reduced the switch densities inside these m...

We present the design of a 12 × 12 photonic crossbar interconnection network constructed using a single three-dimensional acousto-optic crystal. Previous crossbars based on bulk acousto-optic cells require multichannel deflectors with one deflector per optical input; in contrast the design presented here angularly multiplexes these independent deflectors into a single-transducer acousto-optic d...

We consider an N×N input-queued switch with a crossbarbased switching fabric implemented on a single chip. The power consumption produced by the crossbar chip and due to the data transfer grows as NR, where R is the maximum bit rate. Thus, at increasing bit rate, power dissipation is becoming more and more challenging, limiting the crossbar scalability for high performance switches. We propose ...

Based on a decomposition result by Birkhoff and von Neumann for a doubly substochastic matrix, in this paper we propose a scheduling algorithm that is capable of providing service guarantees for input-buffered crossbar switches. Our service guarantees are uniformly good for all non-uniform traffic, and thus imply 100% throughput. The off-line computational complexity to identify the scheduling ...

There are many existing solutions for this, such as dual/triple modular redundancy, DIVA, Bulletproof, etc. Another work, StageNet[1], uses a reconfigurable and adaptable network of replicated and isolated processor pipeline stages to maximize the useful lifetime of a chip. The network is formed by replacing the direct connections at each pipeline stage boundary by a crossbar switch interconnec...

A 32×32 64b self-arbitrating switch fabric called SWIFT achieves a bandwidth of 2.1Tb/s with single cycle arbitration and data transfer la-tency in 65nm technology while operating at 1026MHz at 1.2V. SWIFT co-optimizes arbiter and crossbar logic using a unique fabric architecture that integrates conflict resolution with data routing to optimally use logic and interconnect resources. It spans 0....

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting ...

We use single-walled carbon nanotube (CNT) crossbar electrodes to probe sub-5 nm memory domains of thin AlOx films. Both metallic and semiconducting CNTs effectively switch AlOx bits between memory states with high and low resistance. The low-resistance state scales linearly with CNT series resistance down to ∼10 MΩ, at which point the ON-state resistance of the AlOx filament becomes the limiti...

A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC’s novel reconfigurable device DRP(Dynamically Reconfigurable Processor). In this switch, contexts for the full crossbar and alternative hardware modules, which provide larger bandwidth but can treat only a limited patter...