Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits. Our previous work has suggested that local interconnect effects can be managed through a deep submicron design hierarchy that uses 50 000 to 100 000 gate modules as primitive building blocks. The primary goal of this paper is to examine global interconnect effec...

CMOS data latches used in critical applications must be immune to soft errors such as single event upsets. Existing designs protect the stored data against errors in the internal nodes, but may be vulnerable to transient faults in the control and data lines. The problem becomes more severe as feature sizes decrease. In this paper, we enhance the Dual Interlocked Storage Cell (DICE) to withstand...

This paper proposes issues in highly accurate high frequency noise simulation for deep submicron MOSFETs. Unlike classical RF design, in which a given device with fixed characteristics is used, CMOS RF design permits selection of user specified device geometries as well as matching elements and bias conditions. Therefore, an exhaustive intrinsic noise modeling of MOSFETs across the entire opera...

We discuss the test scheduling problem in this paper. We first provide a historical perspective of the original test scheduling formulation that dealt only with resource conflicts, followed by the consideration of power constraint test scheduling. We then move on to the recent formulations which include dealing with thermal constraint. We explain solutions, their limitations and the challenges ...