the built up layer thickness in secondary deformation zone is one of the important parameters in metal cutting process. the built up layer (bul) is formed in second deformation zone near the tool-chip interface in the back of the chip. this parameter influences the tool life and machined surface quality. this bul should not be confused with the built up edge (bue). the deformation of the bul in...

We have fabricated lab-on-a-chip systems with microchannels separated by integrated membranes allowing for osmotically driven microflows. We have investigated these flows experimentally by studying the dynamics and structure of the front of a sugar solution travelling in 200 microm wide and 50-200 microm deep microchannels. We find that the sugar front travels at a constant speed, and that this...

Polar molecules in selected quantum states can be guided, decelerated, and trapped using electric fields created by microstructured electrodes on a chip. Herein we explore how transitions between two of these quantum states can be induced while the molecules are on the chip. We use CO (a(3) Π(1) , v=0) molecules, prepared in the J=1 rotational level, and induce the J=2←J=1 rotational transition...

nowadays network-on-chips is used instead of system-on-chips for better performance. this paper presents a new algorithm to find a shorter path, and shows that genetic algorithm is a potential technique for solving routing problem for mesh topology in on-chip-network.

In patient with Alzheimer's disease (AD), deposition of amyloid-beta Aβ, a proteolytic cleavage of amyloid precursor protein (APP) by β-secretase/BACE1, forms senile plaque in the brain. BACE1 activation is caused due to oxidative stresses and dysfunction of ubiquitin-proteasome system (UPS), which is linked to p53 inactivation. As partial suppression of BACE1 attenuates Aβ generation and AD-re...

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses ...