Ultrascaled WS 2 field-effect transistors (FETs) fabricated on exfoliated multilayer channels with excellent ON-state and OFF-state performance are reported. Recorded high current ( I xmlns:xlink="http://www.w3.org/1999/xlink"> \scriptscriptstyle ON ) ultralow contact resistance R xmlns:xl...

Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to high demand for large density. Fin-shaped field-effect transistor (FinFET) is one of trending choices memory designers, whi...

Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the bottleneck in power-constrained applications. However, high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” circuits, time storage overhead conventional simulations based on Monte Carlo (MC)...

Abstract: We present the optimization of the manufacturing process of the 5nm bulk-FinFET technology by using the 3D process and device simulations. In this paper, bysimulating the manufacturing processes, we focus on optimizing the manufacturingprocess to improve the drive current of the 5nm FinFET. The improvement of drivecurrent is one of the most important issues in ...

In this paper we present current voltage and trans-conductance model for Dual Material Gate AlGaN/GaN HEMT. Our proposed model demonstrates complete charge control in 2DEG based channel of the device in order to investigate the current-voltage as well as transfer characteristics of the device under various gate and drain biases. The proposed device structure uses GaN material capable to withsta...

− In ultra low power portable devices set towards realizing a long battery life, low energy consumption per operation is the primary design constraint. Hence, operating the circuits in weak inversion or the sub-threshold region, with the subthreshold leakage current acting as the primary computing current, turn out to be a promising solution. Though such a methodology limits the performance in ...

This thesis studied the application of strained-Si technology to RF power LDMOSFETs. Key issues for its implementation were determined to be thermal budget restrictions, gate oxide formation and impact ionization effects. 2D simulations were carried out to explore the design space of the strained-Si LDMOSFET. In order to address the thermal budget restrictions, use of a high-tilt implant for th...

has been developing III-nitride double heterostructures (DHs) with indium gallium nitride (InGaN) channels with a view to high-electron-mobility transistors (HEMTs) [Yi Zhao et al, Appl. Phys. Lett., vol105, p223511, 2014]. The resulting structures boast the highest reported mobility for InGaN channels and superior transport at high temperature, according to the research team. Nitride semicondu...

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In gate stacking, we proposed tri-layer HfO2/TiO2/HfO2 as high-K dielectric and hafnium zirconium oxide (HZO) ferroelectric (FE) layer. The GAA-TFET overcomes thermionic limitation (60 mV/de...

Future MOS transistors may operate near their ballistic limits [1], so it is important to understand ballistic device physics and the prospects for achieving quasi-ballistic operation. In this paper, we explore the device design and physics issues of MOSFETs at the scaling limits using semiclassical and full quantum simulations. The device we presume is a double-gate (DG) MOSFET with symmetrica...