Delta-sigma modulation for analog-to-digital conversion resolves a number of bits logarithmic in the number of modulation cycles, and linear in modulation order. As an alternative to higher-order noise shaping, we present an algorithmic scheme that iteratively resamples the modulation residue, by feeding the integrator output back to the input. This yields a bit resolution linear in the number ...

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the ref...

Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta–sigma data converters because they facilitate delta–sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digit...

This paper presents a new digital servo architecture that reduces power consumption significantly. This paper shows an example of the low power digital servo architecture, which reduces its current almost by 83%, compared to that of conventional digital servo. This architecture applies to the compact disc (CD), Video-CD (VCD), digital versatile disc (DVD), CD-ROM, and DVD-ROM. Through this redu...

This thesis describes the different aspects of the design and implementation of a I2-bit 50M samplesjs pipelined non-binary radix 1.9 analog-to-digital converter. The converter architecture is made up of 14 stages with an interstage gain of 1.9 (non-binary radix). Each stage is made of one fully differential sample-and-hold amplifier (SHA), a I-bit sub-ADC (basically one comparator) and a I-bit...

This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R architecture is used. The DAC was designed i...

We describe a floating-gate trimmed, 14-bit, 250Ms/s current-steered DAC fabricated in a 0.25μm CMOS logic process. We trim the static INL to ±0.3LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm of die area, consumes 53mW at 250MHz, allows on-chip electrical trimming, and achieves 72dB SFDR at 250Ms/s. Introduction Emerging standards for communications systems requ...

Feedback DAC errors in a ∆Σ analog to digital converter are determined by measuring the idle channel output and removing the DAC elements one by one. This method requires simple computation, does not add excess loop delay, and requires no reconfiguration of the ∆Σ modulator. The errors so determined can be used to correct the output codes in the digital domain or the DAC elements in the analog ...

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog...

The utilization of microfluidic "lab-on-a-chip" devices in fundamental medical research, drug discovery and clinical diagnostics has rapidly increased in the past decade. Lab-on-a-chip devices process small volumes of analytes and reagents through on-chip microfluidic signal processing circuits. This paper discusses the implementation of a basic microfluidic circuit block, the concentration dig...