quantum-dot cellular automata (qca) are a promising nanotechnology to implement digital circuits at the nanoscale. devices based on qca have the advantages of faster speed, lower power consumption, and greatly reduced sizes. in this paper, we are presented the circuits, which generate random numbers in qca. random numbers have many uses in science, art, statistics, cryptography, gaming, gamblin...

We describe a mechanically checked correctness proof for the compara-tor sort algorithm underlying a microcode program in a commercially designed digital signal processing chip. The abstract algorithm uses an unlimited number of systolic comparator modules to sort a stream of data. In addition to proving that the algorithm produces an ordered permutation of its input, we prove two theorems that...

Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized k*k reversible gate family is proposed and a 3*3 gate of the family is discussed. Inverter, AND, OR, NAND, NOR, and EXOR gates can be realized by this gate. Implementation of a full-adder circuit using two such 3*3 gates is given. This full-ad...

This paper presents the design, the analysis and the complete characterization of a novel split-path Data Driven Dynamic (sp-D3L) full adder cell in IBM’s 65 nm CMOS process. The split path D3L design style derived from standard D3L allows the design of high speed dynamic circuits without the power overhead of the clock tree while providing significantly higher performance than the D3L due to r...

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand building blocks LCG (Linear congruential generator) based pseudo-random bit generators. Elementary fast, area and power efficient for small sizes. Carry save adder computes addition O(n) time complexity, due to its ripple carry stage. Parallel prefix such as Han-Carlson compute O(log(n)) complexit...

In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically imple...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...

Modulo 2 ÿ 1 adders as fast as n-bit 2’s complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2, 2 ÿ 1, and any other of the form 2 ÿ 1, with k < n, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel t...