Here, we developed a procedure for mitigating thermal hazards in packaged FinFET devices. A monitoring system was installed into devices, based on self-heating impact analysis the and device levels, to allow observation alerting of chip temperature reliability risks. novel algorithm reducing measurement noise by means fluctuation compensation filtering invalid data is presented demonstrated The...

In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate dev...

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluc...

In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium ( $\boldsymbol {\varepsilon }$ -Ge...