Flip and flop splice variants of AMPA receptor subunits are expressed in distinct but partly overlapping patterns and impart different desensitization kinetics to cognate receptor channels. In the absence of specific antibodies, isoform-specific differences in trafficking or localization of native flip and flop subunits remain uncharacterized. We report that in several transfected cell lines, t...

There is no theoretical reason to think that the spin-flip component of the Pomeron is zero. One can measure the spin-flip part using Coulomb-nuclear interference (CNI). Perturbative QCD calculations show that the spin-flip component is sensitive to the smallest quark separation in the proton, while the non-flip part probes the largest separation. According to HERA results on the proton structu...

Abstract: In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digi...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

The latches are simple circuits with feedback from the digital electrical engineering. We have included in our work the C element of Muller, the RS latch, the clocked RS latch, the D latch and also circuits containing two interconnected latches: the edge triggered RS flip-flop, the D flip-flop, the JK flip-flop, the T flip-flop. The purpose of this study is to model with equations the previous ...

This paper enumerates low power, high speed design of D flip-flop. It presents various techniques to minimize subthershold leakage power as well as the power consumption of the

Due to fast growth of portable devices, power consumption and timing delays are the two important design parameters in high speed and low power VLSI design arena. In this paper we presents the comparison of single edge triggered static D flip-flop designs to show the benefit of power consumption ,delay and power delay product on the basis of area efficiency.

This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...

Combination treatment regimens that include topoisomerase-II-targeted drugs, such as doxorubicin, are widely used in the treatment of breast cancer. Previously, we showed that IFN-gamma and doxorubicin cotreatment synergistically induced apoptosis in MDA435 breast cancer cells in a signal transducer and activator of transcription 1-dependent manner. In this study, we found that this synergy was...