The article discusses design of mathematical model buck and boost converter and the analysis of the optimal frequency choice of the PWM signal for IGBT. The converter is dedicated for charging and discharging of hybrid car drive super-capacitor energy storage. The main role of the converter is to optimize energy content in supercapacitor storage used to acceleration and deceleration during driv...

Purpose – The aim of this paper is to improve and adapt cascaded multilevel converters for electric vehicles (EVs) to have all the advantages of these converters and to eliminate its limitations in the use of EVs applications. Specifically, the purpose is to use only a single power source (battery pack, fuel cell, etc.) and generate a higher power-quality than regular multilevel converters. Des...

This study proposes a novel bidirectional-switched-capacitor-based interleaved converter. In view of the shortcomings two well-known unidirectional-switched-capacitor-based converters, this improves such converters through combining structure switched capacitor circuit. The first effort was to overcome drawback Cockcroft–Walton-based converter, whose circuit impedance and ripple cause serious o...

Enhancement of fault ride-through (FRT) capability and subsequent improvement of rotor speed stability of wind farms equipped with doubly fed induction generator (DFIG) is the objective of this paper. The objective is achieved by employing a novel FRT scheme with suitable control strategy. The proposed FRT scheme, which is connected between the rotor circuit and dc link capacitor in parallel wi...

An active filter-based on-chip DC–DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate...

An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain-and offset-compensated opamp is explained. SWIT-CAP simulation...

This paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 μm CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design opera...