Our program involve the synthesis, assembly, and structural and electrical characterization of single crystal Si nanoparticles. The goal of this work is developing high-speed electrical nanoparticle devices. In this article we review the processes needed to demonstrate a vertical transistor built using PtSi as a Schottky barrier source and drain. A surround-gate of Pt is insulated from body of ...

In this paper, we propose and validate a Heterogate DielectricDual Material Gate-Gate All Around, Tunnel Field Effect Transistor (HD-DMG-GAA-TFET). A comparative study for different values of high-k has been done, and it has been clearly shown that the problem of lower ION (which hinders the circuit performance of TFET) can be overcome by using the dielectric engineered hetero-gate architecture...

Flexible transistor active matrix array is fabricated on PEN substrate using all screen-printed gate, source and drain electrodes. Parylene-C and DNTT act as gate dielectric layer and semiconductor, respectively. The transistor possesses high mobility (0.33 cm 2 V -1 s -1 ), large on/off ratio (> 10 6 ) and low leakage current (~10 pA). Active matrix array consists of 10×10 transistors were dem...

NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms. NCL circuits use threshold gates with hysteresis. In this chapter, the transistor-level CMOS design of NCL gates is investigated, and various gate styles are introduced and compared to each other. In addition, a novel approach to design static NCL gates is introduced. The new approach is based on integrati...

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complem...

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well...

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic tran...

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay (VID) g...

The electrical characteristics of germanium p-metal– oxide–semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO2/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO2 as gate dielectric, good interface properties, good transistor characteristics, and about...

The end of the roadmap for planar single-gate (SG) CMOS seems to be drawing nearer as the industry increases research activities in double-gate (DG) and multi-gate (MG) CMOS novel device structures. Therefore, this paper will focus on how to extend the life of planar SG CMOS through 2016 and accelerate the understanding & realization of MG CMOS by 2007 through the use of advanced ion implantati...