The last years have seen the emergence of fault attacks targeting modern central processing units (CPUs). These are analyzed at a very high abstraction level and, due to CPUs complexity, underlying effect is usually unknown. Recently, few articles focused on characterizing faults CPUs. In this article, we focus electromagnetic injection (EMFI) characterization bare-metal implementation. With ap...

Issuing four instructions per cycle, this wo rksta tio n/server processor uses the Visual Instruction Set and a nonblocking memo y system to accelerate multimedia applications. Itrasparc I is a second-generation superscalar processor. It is a high-performance, highly integrated, four-issue superscalar processor based on the Sparc Version 9 64-bit RISC architecture.' We have extended the core in...

CPU flush instruction-based cache side-channel attacks (cache instruction attacks) target a wide range of machines. For instance, Meltdown / Spectre combined with FLUSH+RELOAD gain read access to arbitrary data in operating system kernel and user processes, which work on cloud virtual machines, laptops, desktops, mobile devices. Additionally, fault injection use cache. Rowhammer, is attack that...

As microprocessor complexities and costs skyrocket, designers are looking for ways to simplify their designs to reduce costs, improve energy efficiency, or squeeze more computational elements on each chip. This is particularly true for the embedded domain where cost and energy consumption are paramount. Software instruction caches have the potential to provide the required performance while usi...

Several studies have pointed out that the values produced by the execution of a program’s instructions are often quite repetitive. There are basically two approaches that have been proposed for exploiting this value locality – 1) reusing the results of a prior execution of an instruction, and 2) predicting the value that will be produced by the current execution of an instruction based on the p...

One of the key challenges computer architects and compiler writers are facing, is the increasing discrepancy between processor cycle times and main memory access times. To overcome this problem, program transformations that decrease cache misses are used, to reduce average latency for memory accesses. Tiling is a widely used loop iteration reordering technique for improving locality of referenc...

Nearly all modern computing systems employ caches to hide the memory latency. Modern processors often employ multiple levels of cache, with one or more levels on the same die as the processor core. As performance demands increase, it becomes increasingly important for an on-die cache structure to perform well. Inefficient use of the available cache space can become increasingly costly in terms ...

The quest for time-predictable systems has led to the exploration of new hardware architectures that simplify analysis and reasoning in the temporal domain, while still providing competitive performance. For the instruction memory, the method cache is a conceptually attractive solution, as it requests memory transfers at well-defined instructions only. In this article, we present a new cache an...

A new CMOS microprocessor, the Alpha 21164, reaches 1,200 mips/600 MFLOPS (peak performance). This new implementation of the Alpha architecture achieves SPECint92/SPECfp92 performance of 345/505 (estimated). At these performance levels, the Alpha 21164 has delivered the highest performance of any commercially available microprocessor in the world as of January 1995. It contains a quad-issue, su...

It is vital that the cost of a cache miss be accurately measured in order for many hardware and software optimizations to occur. In this paper we describe a new technique, called pipeline spectroscopy, that allows pipeline delays to be monitored and analyzed in detail. We apply this technique to produce a cache miss ‘spectrogram’, which represents a precise readout showing a detailed histogram ...