Carry-select addition techniques imply the computation of double sum and carry bits with subsequent selection of the correct values, resulting in significant area overheads. This overhead increases massively when the selection scheme is applied to multiple levels in order to further reduce computation time. A recently proposed reduced-area scheme for carry-select adders lowers this overhead by ...

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless,...

Many disturbances can impact gate assignments in daily operations of an airport. Gate Assignment Problem (GAP) is the main task of an airport to ensure smooth flight-to-Gate assignment managing all disturbances. Or, flights schedule often undergoes some unplanned disruptions, such as weather conditions, gate availability or simply a delay that usually arises. A good plan to GAP should manage as...

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS tran...

Circuit delay computation taking into account the existence of false paths represents a significant and computationally complex problem. Existing research work has focused mainly on path sensitization models and algorithms, and on gate and interconnect delay models. Nevertheless, work in these two main areas has evolved separately, and so most path sensitization models and algorithms assume ver...

In this paper, the performance of a CNT-JLTFET under different values of torsional strains of 0, 3, and 5 degrees has been investigated. Simulation has been carried out using non-equilibrium Green’s function (NEGF) formalism in the mode-space approach and in the ballistic limit. The simulation results indicate that, under torsional strain, an increase occurs in the energy band-gap, and thus the...

Discrete gate sizing and threshold assignment are commonly used tools for optimizing digital circuits, and ideal methods for incremental optimization. The gate widths and threshold voltages, along with the gate lengths, can be adjusted to optimize power and delay. This monograph surveys this field, providing the background needed to perform research in the field. Concepts such as standard cell ...

In this work, by means of Monte Carlo simulations, the static and dynamic behavior of isolated-gate InAs/AlSb high electron mobility transistors (Sb-HEMTs) has been studied and compared with experimental results. The influence of the existence of a native oxide under the gate, the value of the surface charges in the gate recess and the possible variation of electron sheet carrier density, ns, h...

time-delay identification is one of the most important parameters in designing controllers. in the cases where the number of inputs and outputs in a system are more than one, this identification is of great concern. in this paper, a novel autocorrelation-based scheme for the state variable time-delay identification for multi-input multi-output (mimo) system has been presented. this method is ba...

Energy consumption of digital circuits has become a primary constraint in electronic design. The increasing popularity of the portable devices like smart phone, ipad, tablet and notebook has created an overwhelming demand for extended battery life of these devices. Numerous methods for energy reduction in CMOS circuits have been proposed in the literature. Power reduction techniques at various ...