The enhancement of quality factor for TE whispering-gallery modes is analyzed for three-dimensional microcylinder resonators based on the destructive interference between vertical leakage modes. In the microcylinder resonator, the TE whispering-gallery modes can couple with vertical propagation modes, which results in vertical radiation loss and low quality factors. However, the vertical loss c...

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed c...

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead ...

A three-dimensional simulation methodology allowing statistical study of the direct tunnelling gate current fluctuations in realistic nano-scale metal–oxide–semiconductor field effect transistors (MOSFETs) is presented. The approach has been applied to study the gate leakage fluctuations due to the combined effect of oxide thickness variation (OTV) and discrete random dopants (RD) in an example...

Technology scaling reduces device threshold voltages to mitigate speed loss due to scaled supply voltages. This, however, exponentially increases leakage power and adversely affects circuit reliability. In this paper, we will investigate the performance degradation in high-leakage digital circuits. It is shown that deep submicron CMOS technologies lead to 60%−70% degradation in noise-immunity d...

Although tremendous progress has been made on the past years on channel estimation in ofdm systems still it is considered as area of concern in wireless communication. A novel channel estimation technique with virtual sub carriers is proposed in this work namely a low-complexity but near-optimal DFT-based channel estimator with leakage nulling is proposed for OFDM systems using virtual subcarri...

The purpose of this paper is to illustrate a physicallybased model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the...

Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for high-performance cache, which...

Although tremendous progress has been made on the past years on channel estimation in OFDM systems still it is considered as area of concern in wireless communication. A novel channel estimation technique with virtual sub carriers is proposed in this work namely DFT Based Channel Estimation for OFDM Systems that maintains Complexity-Performance Trade-Offs and with leakage suppression using virt...

Shallow trench isolation (STI) has become the most promising isolation scheme for ULSI applications. However, the trench isolation suffers from dislocations and oxidation induced stacking faults. Such faults are typically located near trench edges. These STI faults increase the junction leakage current and may turn-on the parasitic STI MOSFET resulting in significant leakage current through the...