نتایج جستجو برای: locked loop pll
تعداد نتایج: 143872 فیلتر نتایج به سال:
The moving average filter-based phase-locked loop (MAF-PLL) can obtain grid synchronization signals accurately under adverse conditions with a large amount of harmonics due to the high filtering capability MAF. However, MAF-PLL cannot achieve fast dynamic response in case frequency drift, phase angle steps, and unbalanced voltage sag. MAF is essentially an FIR filter, its performance hard be ad...
The single-phase phase-locked loop (PLL) is essential for the stable operation and control of grid-connected converters. However, in practical applications, grid voltage usually affected by harmonics dc offset, which will cause errors output PLL. Therefore, using sliding discrete Fourier transform filter (SDFT) as a prefilter, this paper proposes an improved synchronous reference frame PLL with...
Jitter and phase noise properties of phase-locked loops (PLL) are analyzed, identifying various forms of jitter and phase noise in PLLs. The effects of different building blocks on the jitter and phase noise performance of PLLs are demonstrated through a parallel analytical and graphical treatment of noise evolution in the phaselocked loop.
The paper proposes a way of implementing a phase locked loop (PLL) motor speed controller. The main emphasis is on the FPGA implementation of the digital PLL. The closed loop sensing element is an optical tachometer, which outputs an impulse train with a frequency proportional to the motor rotational speed. This impulse train will be synchronized by the PLL to a reference impulse train of a giv...
Speed estimation schemes based on the closed-loop synchronization (CLS) methods for speed-sensorless control of motor drives attract much popularity due to several advantages, example, easy implementation, high flexibility, and acceptable performance. However, most existing CLS-based may suffer from performance degradation during frequency ramps. Considering this, an attempt type-3 phase-locked...
This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and gain control. The PLL consisting of phase frequency detector (PFD), filter, voltage-controlled oscillator (VCO) makes the to be locked at resonant frequency. is modeled by Butterworth–Van Dyke equivalent model motional resistance 72.8 kΩ, 6.19 fF, i...
This paper presents an integrated frequency hopped transceiver based on a subset of the cdma2000 network specifications. The circuit consists of a phase locked loop (PLL) that generates the hopping carriers, local oscillators (LOs) that generate GHz range carrier frequencies, and a series of mixers. It accepts input data in frequency shift keyed (FSK) format, and also outputs received data in F...
In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as tool for credible analysis dynamical properties these circuits, is studied. We refine relevant definitions the hold-in and pull-in ranges related local global stability. Stability steady state charge-pump phase locked loop non-trivial: straight-forward linearization available CP-PLL models may lead i...
Security of cryptographic systems depends significantly on security of secret keys. Unpredictability of the keys is achieved by their generation by True Random Number Generators (TRNGs). In the paper we analyze behavior of the Phase-Locked Loop (PLL) based TRNG in changing working environment. The frequency of signals synthesized by PLL may be naturally influenced by chip temperature. We show w...
The Phase-Locked Loop is used to track an incoming signal and provide accurate carrier phase measurements on GPS receivers. However, the PLL performance is affected by the thermal noise and dynamic stress. In order to resolve the conflict between reducing PLL noise and overcoming the dynamic stress, some compromises must be taken in PLL design. This paper proposes a wavelet packet de-noising te...
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