Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the conte...

An algorithm was developed to estimate aerosol optical depth (AOD) from geostationary satellite data. The 6S radiative transfer computer code was employed to generate a look-up table (LUT) which incorporates several combinations of satellite-derived variables including earthatmospheric reflectivity, atmospheric reflectivity and surface albedo. The parameterization of the satellite-derived atmos...

In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows 81.25% saving of memory blocks ...

Different architectures have been proposed for FPGA implementation of Universal Modulator. The Look up table (LUT) technique is one way of realizing universal modulator. Here the CORDIC is used for efficient realization of Universal Modulator. The coordinate rotation digital computer (CORDIC) algorithm is widely used in various technological fields such as digital signal processing (DSP), biome...

A new approach to enhance the compression performance and execution time of chaos-based joint compression and encryption schemes is proposed. Instead of finding a new method to update the Look-up Table (LUT) in each iteration or using a different method to represent the ciphertext, we use multiple LUTs based on the conditional bi-gram probabilities of two consecutive source symbols occurring in...

In this current fast moving world, getting the information faster is more important. My project makes it happen. SMS4 cipher based on Pipelined Twisted BDD (Binary Decision Diagram) S-box architecture can convert the plain text into cipher text as fast as other S-box architecture. SMS4 is a 128-bit block cipher used in the WAPI standard for protecting data packets in WLAN. In this project S-box...

Technology mapping is the one of tasks performed by CAD systems to implement a logic circuit by FPGA's. It transforms a pre-optimized boolean network into a network of building blocks of the target FPGA by taking the physical restriction (e. g. number of inputs) into consideration. This report summarizes the chapter 3 of [1] which is a comprehensive and exhaustive reference of technology mappin...

This paper presents a discrete device for neural network realized on field-programmable gate arrays (FPGA). A basic element of the implemented neural network is new type of neuron, called Boolean neuron that may be mapped directly to configurable logic blocks (CLB) or to look up table (LUT) of FPGAs. The structure and logic of the Boolean neuron allows a direct representation of the Boolean neu...

We are developing and evaluating a new technique for the extraction of environmental information such as water-column inherent optical properties and shallow-water bottom depth and classification from remotely-sensed hyperspectral ocean-color spectra. Our technique is based on a “look-up-table (LUT)” approach in which the measured spectrum is compared with a large database of spectra correspond...

The secret information, which is embedded in integrated circuit (IC) devices such as a smart card, has the risk of theft by reverse engineering (RE). The circuit design of IC can be stolen by the RE, and the counterfeit can be illegally fabricated. Therefore, the secure IC device requires the circuit architecture protected from the RE attacks. This paper proposes the diffusion programmable devi...