The purpose of this project is to lower the power consumption by reducing the operating voltage of a 32-bit adder, implemented with TSMC035 technology. The delay and power dissipation of the circuit at different voltages were studied and based on the power delay product an optimal voltage of operation was chosen. A level converter circuit was designed, in order to make the circuit compatible wi...

The sustained growth in VLSI technology is fuelled by the continued shrinking of transistor to ever smaller dimension. The benefits of miniaturization are high packing densities, high circuit speed and low power dissipation. Binary multiplier is an electronic circuit used in digital electronics such as a computer to multiply two binary numbers, which is built using a binary adder. A fixed-width...

Abstract A new high-speed and low-power threshold detector is proposed to realize high-performance arithmetic VLSI systems. In a conventional threshold detector with a single supply voltage, the input signal swing of a differential-pair circuit (DPC) is too large, which causes large power dissipation together with a long switching delay. The use of two kinds of supply voltages makes the input s...

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regula...

An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion used reversibility the advancement multilayer 3D circuitry. In modern digital world, selected nano-sized effective alternative widely “CMOS Technology” because all limitat...

The sustained growth in VLSI technology is fuelled by the continued shrinking of transistor to ever smaller dimension. The benefits of miniaturization are high packing densities, high circuit speed and low power dissipation. Binary multiplier is an electronic circuit used in digital electronics such as a computer to multiply two binary numbers, which is built using a binary adder. A fixed-width...

Totally self-checking (TSC) adder design based on the Berger code is proposed for embedded adder cores. A self-checking circuit can execute on-line testing in normal system operation. TSC can immediately detect the error of an electronic system or a computer to avoid the data damaged or the malfunction of a function circuit. Hence, TSC can enhance the reliability of an electronic system, i.e., ...

Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterpa...

This paper presents an efficient asynchronous design methodology for synchronous FPGAs. The mixed synchronous/asynchronous design is the best way to minimize the power consumption of a circuit implemented on a synchronous FPGA. For asynchronous circuit synthesis, Balsa was proposed. However, the problem is that circuits synthesized from Balsa description need a lot of logic resources. To solve ...

This paper presents an overview of datapath realizations of the Hardware neural network models which perform massive parallel operations for best results and real time applications. Digital implemented neural models processing element – adder with low power consumption is proposed for real-time multimedia applications. Proposed adder is illustrated in the 2-3-1 tree layer artificial neural netw...