This study proposes an efficient algorithm for colour image compression with listless implementation based on set partition block embedded coding (SPECK). The objective of this work is to develop an algorithm that exploits the redundancy in colour spaces, low complexity quadtree partitioning and reduced memory requirements. Colour images are first transformed into luminance chrominance (YCbCr) ...

In this paper, a new algorithm is proposed for finding inverse and determinant of a given matrix in one instance. The algorithm is straightforward in understanding and manual calculations. Computer implementation of the algorithm is extremely simple and is quite efficient in time and memory utilization. The algorithm is supported by an example. The number of multiplication/division performed by...

the purpose of this study is to investigate the effect of physical activity onmemory and dynamic balance of elder people. subjects (n=15) were selected asvolunteers. the intervention was performed in an eighteen session period, threetimes a week (each session, 45 minutes). yoga training was performed for mentalrelaxation. wexler test was performed for memory evaluation. seat up test wasused to ...

In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with nested interrupts in a realtime manner. The circular scan test interface facilitates the processes of both test pattern generation and sig...

This study describes  working  memory and developing and validating of an  L1 Persian reading span test for the measurement of working  memory of L1 Persian EFL learners. The test, which included  64  Persian  sentences,  was  developed  based  on  Daneman  and Carpenter’s (1980) reading  span  test.  The  shortcomings  of  the  test  were  identified  and  removed  over  three  pilot studies  ...

This paper presents three parallel procedures implemented in a shared-memory multiprocessor to generate the patterns that allow the testing of digital circuits. The implementation of these procedures in a multiprocessor uses the system memory better than in a distributed-memory multicomputer, since it is not necessary to store the circuit structure in the local memory of each processor, besides...