This paper describes Hot Pages, a software solution for managing on-chip data on the Raw Machine, a scalable, parallel, microprocessor architecture. This software system transparently manages the mapping between the program address space and on-chip memory. Hot Pages combines compile time information to selectively virtualize memory references and to eliminate many cachetag lookups. For many of...

In a wide range of computer controlled systems the issue of security is often of vital importance. System developers invest a vast amount of effort in trying to create a secure system while hackers invest a great deal in trying to breach this security. Many methods of violating security have been devised. Recently, a clever method, based on inserting spurious signals into the clock line of a mi...

We present a methodology for comprehensively evaluating architectural and technological alternatives of the processor, cache hierarchy, system interconnect, and main memory subsystems. We use the methodology to explore the design of an 8-way superscalar microprocessor implemented in 0.3 micron technology and employed in a high-performance workstation. We discuss the cache hierarchy design chall...

are two configurations of a core logic chip set for the DECchip 21064 family of Alpha AXP microprocessors.1 The core logic chip set provides a 32-bit PCI local bus interface, cache/memory control functions, and all related data path functionality to the system designer. It requires minimal external logic. The EB64+ kit is an evaluation and development platform for computing systems based on the...

The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore’s Law is that of removing the large amount of heat generated within the tiny area of a microprocessor. The exponential increase in power density and its direct relation to on-chip temperature have, in recent processors, led to very high cooling costs. Since temper...

T o remain competitive, system-on-chip (SoC) designers must keep pace with silicon technology’s rapid evolution. New communication, consumer, and computer product designs must exhibit rapid increases in functionality, reliability, and bandwidth—and rapid declines in cost and power consumption. All these improvements dictate increasing use of high-integration silicon, in which designers traditio...

This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs HMESFET processor targeted for implementation on a multichip module (MCM) together with cache memories. The CPU architecture, circuit design, implementation, and testing are optimized for a seven-stage instruction pipeline implemented with GaAs super-buffered FET logic (SBFL). We ha...

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combina...

Using a configurable microprocessor to implement low-bit-rate audio applications by tailoring the instruction set reduces algorithm complexity and implementation cost. As an example, this paper describes a Dolby Digital (AC-3) decoder implementation that uses a commercially-available configurable microprocessor to achieve 32bit floating-point precision while minimizing the required processor cl...

While putting most of its emphasis on PowerPC products from its partnership with Motorola, IBM continues to maintain its own line of POWER processors. A relatively small team, in less than a year, took the eight-chip Power2 design (see 071301.PDF) and collapsed it into a single die, delivering a powerful new product. The phenomenal integration provides manufacturing cost savings and, more impor...