A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, a small partial CSA array consisting of only two CSA rows is iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multipli...

According to Larsen [15, p. 13], a function F from a nonvoid subset DF of a commutative semigroup A into A is called a partial multiplier on A if F (D) · E = F (E) ·D for all D, E ∈ DF . Note that if in particular DF is a subsemigroup of A and F ( D · E ) = F (D) · E for all D , E ∈ DF , then F is a partial multiplier on A . A partial multiplier F on A is called total if DF = A . Clearly, the i...

Multipliers and adders are the basic circuits required for implementing any Arithmetic and logic functions in VLSI. Many of the real-time applications like the arithmetic operations in Microprocessor, the filter designing in Signal processing require the multipliers. As the multipliers play a major role in the VLSI designing the power consumption related to them is a parameter to be thought of....

In this paper, we propose two 2’s-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best errorcompensation bias in designing a multip...

This paper proposes a dynamic proportion portfolio insurance (DPPI) strategy based on the popular constant proportion portfolio insurance (CPPI) strategy. The constant multiplier in CPPI is generally regarded as the risk multiplier. Since the market changes constantly, we think that the risk multiplier should change according to market conditions. This research identifies risk variables relatin...

Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterpa...

Low power consumption and small area are some of the most important criteria for design of any high performance systems[i]. So in this paper the best solution to the problem is determined by designing a high speed multiplier chiefly booth multiplier which reduces the number of flip flops and memory size in the design circuitry as compared to conventional serial multiplier. Then implementation o...

An efficient architecture of a reconfigurable Least/Most Significant Bit multiplier for Galois field where , is presented. The proposed multiplier can operate either as a most significant or as a least significant bit first multiplier. The value m, of the irreducible polynomial degree, can be changed and the value of M determines the maximum size that the multiplier can support. This architectu...

This paper presents a new, a highly compact implementation of a 32 32 parallel multiplier based on parallel counters. The new multiplier is designed using the recently proposed Self-Timed Threshold Logic (STTL). The design is based on a direct multiplication scheme using depth 2 (15,4) and (7,3) STTL parallel counters and (4:2) compressors. The proposed parallel multiplier reduces the partial p...

Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF (2) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m + 1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell ...