An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was opera...

Comparing the performance of a set of activities or organizations under uncertainty environment has been performed by means of Fuzzy Data Envelopment Analysis (FDEA) since the traditional DEA models require accurate and precise performance data. As regards a method for dealing with uncertainty environment, many researchers have introduced DEA models in fuzzy environment. Some of these models ar...

In applications like weather monitoring, remote sensing, seismic signal processing etc, the boundaries and sharp features of the images have to be enhanced to obtain useful results and interpretations. The two dimensional(2D) highpass filters are used for such image processing applications. A direct design of the 2D high pass filter using frequency transformation has not been reported in the li...

A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5μm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of mul...

Reversible logic has attracted tremendous interest among the researchers in low power VLSI field due to their simple structure and improved energy efficiency. In this paper, the implementation of an 8-bit low power multiplier based on reversible gate technology is reported. The structure of the reversible gate multiplier consists of following components: the first part is the reversible partial...

We show that the assumption n1 > λ in the Second Multiplier Theorem can be replaced by a divisibility condition weaker than the condition in McFarland’s multiplier theorem, thus obtaining significant progress towards the multiplier conjecture.

The general goal of this paper is to identify a transformation group that can be used to describe a class of feedback interconnections involving subsystems which are modeled solely in terms of Chen–Fliess functional expansions or Fliess operators and are independent of the existence of any state space models. This interconnection, called an output affine feedback connection, is distinguished fr...

Article history: Received Accepted Available online 20 Nov. 2014 19 Dec. 2014 25 Dec. 2014 Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed. Row-bypassing multiplier, column-bypassing multiplier, 2-Dimensional bypassing multiplier and braun multipliers are implemented in CMOS and GDI tec...

In this paper we propose a new structure for multiplication using optimal normal bases of type 2. The multiplier uses an efficient linear transformation to convert the normal basis representations of elements of Fqn to suitable polynomials of degree at most n over Fq. These polynomials are multiplied using any method which is suitable for the implementation platform, then the product is convert...