increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. ...

Application mapping is one of the key problems of Network-on-Chip (NoC) design. It maps the cores of application to the processing elements of the NoC topology. This paper presents a novel approach for NoC application mapping, which uses adaptive genetic algorithm (AGA) in the mapping. The proposed approach adaptively varies the probabilities of crossover and mutation operators in genetic algor...

The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the Æthereal NoC, address the software challenges by making the sy...

Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies...

Development of a new regular topology for Network on Chip (NoC) is a challenging task, as the proposed design should meet the application specific targets of latency, throughput, area, and energy as well. A suitable routing over newly proposed topology must handle congestion and provide deadlock free transmission. This paper discusses design, implementation of five port regular NoC structure (e...

Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. (May 2011) Yu Yang, B.S., Zhejiang University; M.S., Zhejiang University Chair of Advisory Committee: Dr. Jiang Hu Network-on-Chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple voltage-freque...

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In ...

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes ...

Multiprocessor system on chip (MPSoC) platform is an innovative trend of System on Chip (SoC) that enhances system performance. Demanding quality of service parameters and performance metrics, especially in mobile applications, are leading to the exploration of even more innovative architectures for SoC. These will have to incorporate highly scalable, reusable, predictable, cost and energy effi...