Embedded systems sometimes experience transient overloads due to workload bursts. Such systems have to be designed to take timely reactions at the occurrences of unexpected situations. The development of smart techniques that focus the available computing power on these urgent events and at the same time, slow down the processing frequency during inactive periods could be the key for preserving...

C-based cycle-accurate simulations are used to evaluate the performance of a Network-On-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformlydistribute...

The aim of this Chapter is to present a highly flexible reconfigurable NoC solution for commercial FPGAs on one side, and on the other side, to provide an innovative approach for fast NoC emulation. The reconfigurable on-chip communication solution that is proposed in this chapter is capable of being reconfigured by means of adapting routers, network interfaces and cores themselves. The main di...

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network-on-Chip (NoC) paradigm is an interesting ...

Network on-Chip (NoC) is an interconnect fabric to connect sub-system blocks on a chip. The NoC should provide high bandwidth and low latency, should consume low energy, and should be compact. However, all these requirements are at odds and require tradeoffs at all levels. In this chapter, we discuss issues and challenges for future NoCs with demands for high bandwidth and low energy. Next, we ...

Multicast communication has increasingly become common and indispensable for Network-on-Chip (NoC). Router is the key unit of NoC, but few of its implementations provide multicast communication directly. In this letter, we design a tree-based multicast router using differentiated subnetwork. Also, we propose a new deadlockfree routing algorithm to overcome the complex deadlock problem on NoC wh...

Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may ...

Due to continuous advancements in modern technology processes which have resulted in integrated circuits with smaller feature sizes and higher complexity, current system-on-chip designs consist of many different components such as memories, interfaces and microprocessors. To handle this growing number of components, an efficient communication structure must be provided and incorporated during s...

Chip MultiProcessors (CMPs) have become the primary method of build high-performance microprocessors. Besides speed, major elements such as processing elements and network on chip, allocation and management of on-chip processors are also important factor to achieve high efficiency of future CMPs. In this paper, the authors study a Processor Allocator (PA), especially the issue of its memory uti...

Routing strategies have a key role on communication and performance of the on-chip interconnection networks. Typically, each routing technique can be divided in two parts: output selection and input selection. Several efforts have been done attempting to improve output selection part. But this paper focuses on the improvement of input selection part and investigation of its impact on routers, r...