In-memory computing (IMC) has been widely accepted to be an effective method improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, 8T array with configurable word lines is proposed, where the arranged rows, following traditional storage pattern, the...

In this paper we investigate low weight and fan-in neural networks for the precise computation of some basic arithmetic operations. First we assume one bit per serial cycle LSB first operand reception and introduce a pipeline network performing serial binary addition in O(n) time constructed with 11 threshold gates, a maximum weight of 2 and a maximum fan-in of 4. Further we prove that serial m...

Value reuse improves a processor’s performance by dynamically caching the results of previous instructions and reusing those results to bypass the execution of future instructions that have the same opcode and input operands. However, continually replacing the least recently used entries could eventually fill the value reuse table with instructions that are not frequently executed. Furthermore,...

Recently, a rst version of our GEMM-based level 3 BLAS for superscalar type processors was announced. A new feature is the inclusion of DGEMM itself. This DGEMM routine contains inline what we call a level 3 kernel routine, which is based on register blocking. Additionally, it features level 1 cache blocking and data copying of sub-matrix operands for the level 3 kernel. Our other BLAS's which ...

Minimal-interval semantics [5] associates with each query over a document a set of intervals, called witnesses, that are incomparable with respect to inclusion (i.e., they form an antichain): witnesses de ne the minimal regions of the document satisfying the query. Minimal-interval semantics makes it easy to de ne and compute several sophisticated proximity operators, provides snippets for user...

This paper presents a general theory for developing new Svoboda-Tung (or simply NST) division algorithms not suuering the drawbacks of the \classical" Svoboda-Tung (or simply ST) method. NST avoids the drawbacks of ST, by means of a proper recoding of the two most signiicant digits of the residual before selecting the most signiicant digit of this recoded residual as the quotient-digit. NST rel...

Lesion and brain-imaging studies have implicated the prefrontal and parietal cortices in arithmetic processing, but do not exclude the possibility that these brain areas are also involved in nonarithmetic operations. In the present study, we used functional magnetic resonance imaging to explore which brain areas contribute uniquely to numeric computation. Task difficulty was manipulated in a fa...

We have built an interpreter for the array programming language J. The interpreter exploits implicit data parallelism in the language to achieve good parallel speedups on a variety of benchmark applications. Many array programming languages operate on entire arrays without the need to write loops. Writing without loops simplifies the programs. Array programs without loops allow an interpreter t...

A technique, based on the residue number system (RNS) with operands in the diminished-1 number system, has been used in several applications which include digital signal processing (DSP), implementation international data encryption algorithm (IDEA), Fermat number transform (FNT), and so on. For implementation of these techniques, several designs for modulo 2+1 diminished-1 arithmetic blocks ha...

Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Com...