The IEEE 754 single precision floating point multiplier uses reversible exponent adder to accomplish multiplication operation. The REA is designed and implemented using reversible logic gates like Peres gate and TR gate. Reversible logic is used to reduce the power dissipation compared to classical logic and it can also reduces the information loss so which finds application in different fields...

It is shown that optical rectification in biased quantum wells using specially shaped optical pulses can be used to generate quasi-half-cycle THz electromagnetic pulses. Namely, we investigate THz generation by pulses incorporating a rapid pi phase shift. We further explore the potential of this scheme for high-repetition-rate quasi-half-cycle THz pulse generation.

In this paper, we propose a leakage reduction technique. Because high leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits. Sub threshold leakage current plays a very important role in power dissipation. So to reduce the sub threshold leakage current we proposed an adaptive voltage level (AVL) technique. Which optimize the overa...

In this paper, a three ring-resonator serially coupled is considered as an optical filter. We are going to improve the performance of the designed optical filter by increasing the quality factor and finesse of filtered wavelengths. The first and last rings are coupled to the bus waveguides that carry the input and output fields. The effect of coupling parameters and ring radii on the filtering ...

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometrydependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full ...

In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional sig...