We describe the high-level synthesis of scalable 1 parallel architectures implementing in niteimpulse response (IIR) lters using multi-chip module (MCM). Our approach is based on a new class of parallel schedules for computing mth-order IIR lters, called regular schedules. The simplicity of the regular schedules facilitates characterization of their inter-processor communications, which is gene...

We obtain a Calabi-Yau type volume growth estimates for complete noncompact self-shrinkers of the mean curvature flow, more precisely, every complete noncompact properly immersed self-shrinker has at least linear volume growth.

MPP, SMP, clustered SMP, NUMA, data parallelism, sharednothing and shared-everything architectures. Can you explain these buzzwords? You should be able to, because there’s a paradigm shift coming. It is proven technology today to combine dozens or hundreds of CPUs together to build a supercomputer, and many companies are using them to host Decision Support Systems that exploit multi-terabyte da...

We propose a methodology to address the programmability issues derived from emergence of new-generation shared-memory NUMA architectures. For this purpose, we employ dense matrix factorizations and inversion (DMFI) as use case, target two modern architectures (AMD Rome Huawei Kunpeng 920) that exhibit configurable topologies. Our pursues performance portability across different configurations b...