An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

A 6.0-13.5 GHz Alias-Locked Loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fV CO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a fe...

Substrate integrated waveguides (SIWs) have been proposed and applied to develop a two-way out-ofphase power divider in this paper. This newly proposed structure shows good performance in wide frequency range from 8.6 GHz to 10.6 GHz. The proposed multilayer SIW out-of phase power divider consists of two layer of substrates of Rogers 5880 with thickness of 0.508 millimeters. The input at the up...

ELECT A new two-dimensional oscillator array-based injection-locked frequency divider is proposed. Instead of using the conventional analogue tuning technique or the one-dimensional delay chain, a two-dimensional array is implemented to digitally and precisely control the total delay in the oscillator core. This makes it possible to achieve a programmable delay, hence attaining potential progra...

The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than −187.0 dBc/Hz of FoM, can be extended from 6.5–12.5 GHz to 1.5–12.5 GHz. The propose...

A cascade of two directional couplers with a relative phase shift between them, serves as an optical power divider. Simple analytic universal design rules for selecting the appropriate net coupling strength in each device, and for the phase shift, yield maximally flat response in terms of deviations in wavelength, polarization, or uniform fabrication errors, and are applicable to any power divi...

We propose a technique with clear guidelines to design a compact planar Wilkinson power divider (WPD) for ultra-wideband (UWB) applications. The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional power divider with varying-impedance profiles governed by a truncated Fourier series. Such non-uniform transmission lines (NTLs) are obtained t...

This paper analyses substrate-related spurious tones in fractional-N phaselocked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these ...