Microwave photonic processors leverage the modern photonics technique to process microwave signal in optical domain, featuring high speed and broad bandwidth. Based on discrete components, different are reported. Due limitation of opto-electronic most realized designed serve a specific demand. With booming development integrated circuits (PICs), new possibilities opened for implementation proce...

Reconfigurable computing (RC) is becoming increasingly popular as it bears the promise of combining the flexibility of software with the performance of hardware. Although the huge reconfiguration latency of the available FPGA platforms is a well-known shortcoming of the current Field-programmable Custom Computing Machines (FCCMs), little research in instruction scheduling has been undertaken to...

This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was defined as a set of abstract assertions. A...

In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. ...

This paper presents a new approach that is complete functionality of SDR implemented in an Application Specific Instruction Processor (ASIP). In this paper, we discuss the details of design of architecture for an ASIP for SDR with a single bus and dedicated paths. We explain the instruction-set design for implementation of the SDR functionality and their instruction formats. We have used System...

A main objective in code generation for ASIPs is to develop retargetable compilers in order to permit exploration of di erent architectural alternatives within short turnaround time. Retargetability requires that the compiler is supplied with a formal description of the target processor. This description is usually transformed into an internal instruction set model, on which the actual code gen...

The demand for high performance embedded processors, for consumer electronics, is rapidly increasing for the past few years. Many of these embedded processors depend upon custom built Instruction Ser Architecture (ISA) such as game processor (GPU), multimedia processors, DSP processors etc. Primary requirement for consumer electronic industry is low cost with high performance and low power cons...

Stringent power and performance constraints, coupled with detailed knowledge of the target applications of a processor, allows for application-specific processor optimizations. It has been shown that application-specific reconfigurable hash functions eliminate a large number of cache conflict misses. These hash functions minimize conflicts by modifying the mapping of cache blocks to cache sets....

Software-Defined Radio (SDR) allows the signal processing components of a wireless device to be implemented in a reconfigurable processor. Recent research has focused on using general-purpose processors (GPPs) for performing signal processing in SDRs. While older GPPs lacked the processing power required for implementing many of the modern, commercial, digital waveforms, newer GPPs offer promis...