Reducing absorber layer thickness below 500 nm in regular Cu(In,Ga)Se2 (CIGS) solar cells decreases cell efficiency considerably, as both short-circuit current and open-circuit voltage are reduced because of incomplete absorption and high Mo/CIGS rear interface recombination. In this work, an innovative rear cell design is developed to avoid both effects: a highly reflective rear surface passiv...

This application note for the LMK04000 family of clock conditioners covers the design of an external oscillator circuit using a crystal resonator. The LMK04000 family supports either an external, self-contained VCXO module or a discretely implemented voltage controlled crystal oscillator based upon a crystal resonator. The LMK04000 family features an internal loop amplifier that enables the imp...

This paper proposes an efficient architecture independent packing method for commercial FPGA. All specific logics of commercial FPGA such as carry chain arithmetic, x-LUT, are pre-designed into reference circuits according to its architecture. Due to complex architecture of contemporary FPGA, to enumerate all reference circuits in a fine-grain manner is impractical. To overcome this problem, co...

This paper presents the implementation of a built-in current sensor for DDQ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) ena...

The paper describes a CMOS voltage reference design that uses the temperature dependence of NMOS and PMOS threshold voltages to form a temperature-insensitive reference. No diodes or parasitic bipolar transistors are used. The circuit architecture accommodates a wide range of output voltages. A test chip is fabricated using a 0.5mm CMOS process. The prototype achieves a temperature coefficient ...

A sub-1-V CMOS band gap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with vthn=vthp=0 9 V at 0 C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 A. A temperature coefficient of 15 ppm/ C from 0 C to 100 C is recorded after trimming. The active area of the circuit is abo...

Abstract. This document describes objectives and method used to characterize DTMOST structures in the 0.13μm CMOS technology. The temperature dependence of the Id(Vgs) relationship is measured and parameterized into a simple mathematical model. On the basis of this model performances of two basic Bandgap reference (BGR) circuits have been evaluated. The classical voltage summing BGR circuit dem...

A curvature compensation technique for bandgap voltage references that utilizes an adaptive reference temperature is presented. This compensation technique is intended for high-resolution temperature-stable analogdigital converters. A test circuit had been designed in a 0.6 μm CMOS technology to implement this technique. The reference voltage has a simulated temperature coefficient of 2.3 ppm/ ...