This paper presents a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates. A modified Linear Feedback Shift Register is designed in which power consumption is reduced by deactivating the...

We present a simple construction of a small probability space on n bits for which any k bits are almost independent. The number of bits used to specify a point in the sample space is O(log log n + k + log ~), where e is the statistical difference between of the distribution induced on any k bit locations and the uniform distribution. This is asymptotically comparable to the construction recentl...

Sum-product message passing (belief propagation) was recently extended to messages/summaries with some nontrivial Markov structure. In this paper, a general update rule for Markov-structured messages is proposed, and further experimental results are presented for the synchronization of noisy linear-feedback shift register (LFSR) sequences.

We determine the imbalances of the keystreams produced by Achterbahn-80 and Achterbahn-128 in two different ways. The number of cyclically inequivalent keystreams produced by the keystream generators of Achterbahn-80 and Achterbahn-128 is determined. An abstract model for the keystream generator of a primitive NLFSR combination generator is used to justify the correlation attack introduced in [...

We study algebraic feedback shift registers (AFSRs) based on quotients of polynomial rings in several variables over a finite field. These registers are natural generalizations of linear feedback shift registers. We describe conditions under which such AFSRs produce sequences with various ideal randomness properties. We also show that there is an efficient algorithm which, given a prefix of a s...

A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of phy...

The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can be integrated with recent, commercial DFT techniques, LP-TPG for in-field testing and in-field diagnostic data collection. To find maximum faults, structural diagnosis is used which does reveal the diagnostic information. A new low power test pattern generator using a linear feedback shift regi...

This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The trang5ormation is performed by a small amount of mapping logic that decodes sets of patterns that don't detect any new faults and maps them into patt...

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