In this paper, we propose a new architecture of non-volatile Flip-Flop based on ReRAM unipolar resistive memory element (RNVFF). This architecture is proposed in the context of power-down applications. Flip-Flop content is saved into ReRAM memory cell before power-down and restored after power-up. To simulate such a structure a compact model of unipolar ReRAM was developed and calibrated on bes...

In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed de...

The AMPA-type glutamate receptor (AMPAR) subunit composition shapes synaptic transmission and varies throughout development and in response to different input patterns. Here, we show that chronic activity deprivation gives rise to synaptic AMPAR responses with enhanced fidelity. Extrasynaptic AMPARs exhibited changes in kinetics and pharmacology associated with splicing of the alternative flip/...

Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulsetriggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. First, a simple two-transistor AND gate design is used to reduce the ci...

This paper enumerates low power, high speed design of TSPC (True Single Phase Clocking) D flip-flop having less number of transistors. This technique allows circuit to achieve lowest power consumption with minimum transistor count. Design of low power device is now an essential field of research due to increase in demand of portable devices. In the circuit as the scaling increase the leakage po...

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous ...

Radiation effects account for increasing soft error occurrences in deep submicron circuits. A method for calculating an upper bound for the width of an erroneous pulse that may reach a flip flop or a primary output is presented. This is required in order to determine pulse removal (PR) circuit characteristics for error correction at each flip flop or primary output side. Key-Words: Soft errors,...

In this paper we propose, experimentally realize and study possible applications of a new type of logic element: random flip-flop. By definition it operates similarly to a conventional flipflop except that it functions with probability of 1/2 otherwise it does nothing. We demonstrate one practical realization of the random flip-flop based on optical quantum random number generator and discuss p...

In this paper a technique is proposed to reduce the power consumption in clock distribution networks. Power has become a major issue in most VLSI designs. Power distribution in VLSI differs from product to product. However it is interesting to note that clock system and logic part itself consume most of total chip power. In practise a large portion of clock distribution network (CDN)s and flip ...

Alamethicin is a hydrophobic antibiotic peptide 20 amino acids in length. It is predominantly helical and partitions into lipid bilayers mostly in transmembrane orientations. The rate of the peptide transverse diffusion (flip-flop) in palmitoyl-oleyl-phosphatidylcholine vesicles has been measured recently and the results suggest that it involves an energy barrier, presumably due to the free ene...