We describe the parallelization of sequential circuit test generation on an Ethernet-connected network of SUN workstations. We use the observations of the previous work to execute the program in two phases. All processors simultaneously run the test generation program, Gentest. In the rst phase, the fault list is equally divided among processors, each of which derives tests for targets from its...

Current paper presents a comparative study of popular test pattern generation approaches based on three tools: a genetic algorithm test generator GATEST, a deterministic logic-level tool HITEC and a hierarchical tool DECIDER. The main reason for this study was to find out, which fault types are likely to be covered by different approaches. Additional motivation for the work was to find guidelin...

Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subse-quences that start and end on the same states may be removed if necessary and suucient conditions are met for...

The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as execution times pose an additional problem. Parallel implementations can potentially provide signi cant speedups while retaining good quality results. In this paper, we present three parallel genetic algorithms for simu...

Achterbahn stream cipher is proposed as a candidate for ECRYPT eSTREAM project which deals with key of length 80-bit. The linear distinguishing attack,which aims at distinguishing the keystream from purely random keystream,is employed to Achterbahn stream cipher. A linear distinguishing attack is based on linear sequential circuit approximation technique which distinguishes statistical bias in ...

Scan paths an: generally added to a sequential cileuit in a final design for testability step. We present an approach to incorporate the behavior of a scan path during circuit synthesis. thus avoiding to implement the scan path shift register as a separate structural entity. The shift transitions of the scan path an: trcalCd as a pan of the system functionality. Depending on the minimization st...

Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a b...

In the past, the major concerns of the VLSI designer were area, performance, and cost; power consumption considerations were mostly of secondary concern. In recent years, however, this trend has begun to change, and, increasingly, power consumption is being given comparable weight to area and speed in VLSI design (Rabaey and Pedram 1996). One reason is that the continuing increase in chip scale...

ÐTwo fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and if sufficient conditions are met ...