Introduction p1 1 Background p2 a) The EKV MOS Model Formulation and Usage p2 b) The Switched Current Memory Cell Principle p4 2 Tips on selecting simulator parameters for a discrete-time simulation p6 3 Example 1Regulated Cascode Memory Cell (saturated) p6 4 Example 2 SI track-and-hold cell, weak/moderate inversion p8 5 Issues on higher-level modeling p11 6 Conclusions p11 7 References p11

This paper presents a nano-watt bandgap voltage reference (BGR). The self-cascode structure is provided as proportional-to-absolute-temperature (PTAT) voltage. Due to the low slope of PTAT voltage, divider consisting five similar MOSFET transistors presented. resulting output will be one-fifth complementary-to-absolute-temperature and four-fifths All MOSFETs are standard CMOS biased in sub-thre...

Despite great progress of lab-on-a-chip (LoC) technology platforms in the last 30 years, there is a lack standardized microfluidic components, real on-chip automation and progressive functional scalability fluidic circuits. Hydrogel-based circuits have high scaling potential provide automation, but are complex system design. An advanced circuit concept for planar chip architectures, originating...

The improvement of a conventional Gyrator-C active inductor consisting of common-emitter configured and common-collector configured with resistance feedback is presented. The fixed passive resistor is replaced with tunable active resistor (TAR) to enhance the adjustability of the active inductor. Multi-regulated Cascode (MRC) circuit is applied to boost quality factor Q. Compared with the conve...

The problems resulting from the use of nano-MOSFETs in design operational trans-conductance amplifiers (OTAs) lead to an urgent need for new techniques produce high-performance metrics OTAs suitable very high-frequency applications. In this paper, enhancement and equations proposed single-stage folded-cascode (FCOTA) are presented its various performance metrics. FCOTA adopts (FC) current sourc...

This open-loop gain enhancement circuit in 1.2pm CMOS does not require cascode or long-channel transistors, thus maximizing output swing and input common-mode range [1,21. Since gain enhancement is achieved not by increasing output resistance, but by matching main and replica amplifiers, high effective open-loop gain is maintained even with resistive loads. This circuit can be used with any tra...

In this paper, a low-power adaptive low noise amplifier (LNA) is presented. The LNA is based on a bipolar cascode topology, uses inductive source degeneration and emitter area scaling to achieve noise and input-impedance matching simultaneously. The input impedance and the noise factor were simulated as function of the bias collector current and the results show that both are approximately cons...

A circuit technique to correct Vdd/PM distortion and improve efficiency as supply modulation of cascode class-E PAs has been proposed. The experimental result shows that the phase distortion can be improved from 20 degrees to 5 degrees. Moreover, a system co-simulation result demonstrated that the EVM can be improved from −17 dB to −19 dB. key words: envelope elimination and restoration (EER), ...

of photodiode and transimpedance amplifier on a 12.4 Moisture Sensitivity and Soldering. narrowly-focused beam falling only on the photodiode provides improved settling times from allanalog circuits to data conversion base circuits. Q1 and Q2 form a "cascode" amplifier circuit. To compensate for the high-frequency rolloff of the photodiode, U1B is configured as Daylight modifications will drama...

Superharmonic injection locking is investigated in a new theoretical approach. Low power frequency dividers are designed using injection locked oscillators with cascode transistors. The Rockwell 0:5 m CMOS process is used to design a 3mW injection locked frequency divider in the 1800MHz frequency range. A 200MHz maximum locking range is achieved in simulations. 2SC3302 TOSHIBA NPN transistors a...