The recently developed Auger Voltage Contrast (AVC) method is an electronic probing technique for rapid delineation of pn-junctions. The simulation of AVC measurements can improve the understanding of the involved physics and facilitate the development of procedures for automatic extraction of the junction position from measurement data. This paper describes the simulation of AVC measurements u...

We describe here two approaches to model the quantum effects that can no more be neglected in actual and future devices. These models are the Schrödinger-Poisson and Density-Gradient methods fully integrated in the device simulator ATLAS. Simulations based on such methods are compared to each other on electron concentration and C-V curves in a MOS-capacitor.

After the excellent performance achieved by normally-on AlGaN/GaN high electron mobility transistors (HEMTs), research focus has shifted to normallyoff structures. We explore the advantages offered by the recessed-gate technique using our two-dimensional device/circuit simulator Minimos-NT. Excellent agreement with experimental data is achieved, and theoretical AC performance for different rece...

Generation–recombination noise associated with bulk defect levels in silicon is modeled in a partial differential equation-based device simulator to study the maximum allowable defect density that guarantees generation-recombination (g–r) noise-free operation in the presence of hotcarrier effects and space-charge injection.

We develop the major steps taken to map a realistic spike timing-dependent plasticity (STDP) model into digital hardware architecture. Several types of mappings are implemented and tested on FPGA device. We compare their applicability to a real-time spiking neural network (SNN) simulator running in biological time-scale. Keywords—Spiking neural network, STDP, realistic models, real-time process...

An approach to increase the capabilities of integrated circuit nonvolatile memory is to take advantage of the hysteresis in the polarization of ferroelectric materials. For a rigorous analysis of this and similar devices a suitable model for the ferroelectric effects has been developed. We describe this model and show the results of its implementation into a device simulator.

A numerical simulator for the calculation of redistribution of low dopant diffusion in silicon has been developed in threedimensional(3D) geometry. The diffusion behavior of boron is investigated by using three mask structures and changing the contact hole sizes. The results of calculations show that 3D diffusion effects will be very important in the development of submicron process and small d...

Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.

A laboratory-testable, solid-state Maxwell demon is proposed that utilizes the electric field energy of an open-gap p-n junction. Numerical results from a commercial semiconductor device simulator (Silvaco International – Atlas) verify primary results from a 1-D analytic model. Present day fabrication techniques appear adequate for laboratory tests of principle.

A 2D analytical model for the calculation of the subthreshold slope has been derived for deep-submicron Fully-Depleted SO1 MOSFET's using a Green's function solution technique. The accuracy of the equations has been verified by a 2D numerical device simulator. It is shown that the analytically derived model for the subthreshold slope is in good agreement with 2D numerical simulation data.