With the rapid advancement of CMOS technologies, nano-scale latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node (QNUs). The is mainly constructed from three dual-interlocked...

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...

The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, an...

Now a day's one of the most crucial issues in the field of FPGAGs, especially in SRAM FPGAs is single event upsets. One of the most effective methods to decrease these errors is using three dimensional FPGAs. This paper presents evaluation and mitigation of SEU cost on six layers three-dimensional (3D) FPGAs. The evaluation results show that SUE rate decrease about 67% on six layers 3D FPGAs. W...

Digital Signal Processors (DSP) embedded in FPGAs are irradiated with heavy ions in order to further understand the impact of particle-induced Single Event Effects (SEE) to their functionality. SEE upset duration and start-time measurements taken of various DSPs simultaneously during irradiation experiments provide a portrait of the various contributing upset mechanism as well as on-orbit rate ...

The radiation effects in electronic parts are called single-event effects, which deemed to be critical for space missions. This paper presents the Single Event Upsets that were observed an onboard memory device of Low Earth Orbit “Flying Laptop” satellite mission during its in-orbit operation. carefully mapped on orbital itself and their root causes investigated together with rates occurrence. ...

プロセスの微細化に伴い、ソフトエラーに代表さ れる一過性のエラーが増加している。ソフトエラー は宇宙空間や SRAMの問題であったが近年では地上 でもソフトエラーの対策が必要となってきている。地 上でのソフトエラーの主要因は高エネルギー中性子 である。高エネルギー中性子が基板の Si原子に衝突 すると 2次イオンが生じる。2次イオンが拡散層の 近傍を通過すると拡散や空乏層の電界によるドリフ トにより拡散層に電子または正孔が集まる。この電 子または正孔によりドレインの電荷が変化して出力 が反転する。 ソフトエラーは高エネルギー中性子が衝突する場 所によって 2 つに分けられる。1 つは FF、SRAM に衝突して直接保持データを反転させる SEU(Single Event Upset)であり、もう 1つは組み合わせ回路部 分に衝突してパルスを発生させる SET(Single Event...

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., voters...