In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...

The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design cryogenic circuits. Previous research on mainly focused standard (SVT) and (LVT) MOSFETs. In this paper, we characterize within temperature range from 300K 4.2K. Vth increases up ~0.25V (W/L=10um/10um) improved subthreshold swing (SS)~14.30mV/[email protected]. off-state current (Ioff) gate-induced drain...

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This pap...

Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/ decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitanc...

A 135mV 0.13W process tolerant 6T subthreshold DTMOS SRAM in 90nm technology" Abstract Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply β-ratio modulation technique. DTMOS SRAM array fabricated in 90nm technology ope...

Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal i...

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-submicron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The...

Abstrac t  As Complementary Metal-Oxide-Silicon (CMOS) technology scales its critical dimensions, it imposes negative impacts on digital circuit performance mainly in two aspects: leakage and variability. It is widely believed that Static Random Access Memory (SRAM), among all digital circuits, is most susceptible to these impacts. Attempting to accommodate leakage and process variability in a...

With CMOS scaling into the Sub-100nm regime, the supply and the threshold voltages need to be scaled proportionately. This necessitates addressing of low power CMOS device design issues. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to addressing the problems associated with device scaling for low power CMOS. This work focuses on the ...

This paper presents a novel type of nanoarchitecture which is both device and circuit independent. The starting idea is that computations can be performed in three fundamentally different ways: entirely digital (using Boolean gates), entirely analog (using high precision analog circuits), or mixed (using both digital and low precision analog circuits). The boundaries between these are sometimes...