While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudorandom based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this paper is to discuss how a recently propos...

This paper briefly reviews on-line built-in self-test (BIST) and shows its importance in concurrent checking. Then a new approach for the design of deterministic BIST hardware test generators is presented. The approach uses high-level models of circuits to identify the classes of tests needed for complete coverage of faults. The test generator is then designed with the following goals: scalabil...

Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to optimize test length with higher fault coverage in scan-BIST circuits. New test pattern generators (TPG) are proposed to generate weighted random patterns and controlled transition density patterns to facilitate efficient scan-BIST implementations. We achieve reduction in test application time wi...

We present design of a two-dimensional (2-D) discrete cosine transform (DCT) circuit with built-in self-test (BIST) capability. After modifying an existing fast 2-D DCT algorithm to make it more flexible, we synthesized the data path and the controller using our high-level BIST synthesis tool and incorporated scan design to other modules. Our design achieves high fault coverage at small cost of...

This paper presents a BIST architecture, based on a single micro-programmable BIST Processor and a set of memory Wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.

This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques.

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not onlyMarch algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be i...

Very Large Scale Integration (VLSI) has made an extraordinary effect on the development of integrated circuit technology. It has not only decreased the dimension and the price but also improved the complexness of the circuits. There are, however, prospective issues which may slow down the efficient use and development of upcoming VLSI technology. Among these is the issue of circuit testing, whi...

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-differenc...

Design modifications to improve testability usually introduce large area overhead and performance degradation. One way to reduce the negative impact associated with improved testability is to take testability as one of the constraints during high-level design phases so that systems are not only optimized for area and performance, but also from the testability point of view. This thesis deals wi...