In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplica...

The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Rec...

This paper proposes a method to reduce static power consumption in Adiabatic logic circuits based on Complementary Pass transistor Adiabatic Logic (CPAL) operated by two phase power clocks. We are applying power gating MTCMOS technique to reduce static power consumption in CPAL circuits. We tested MTCMOS power gating technique on 4-bit ripple carry adder to observe effect of static power reduct...

We propose a methodology for the speciication, veriication, and design of hybrid systems. The methodology consists of the computational model of Concrete Phase Transition Systems (cptss), the speciication language of Hybrid Temporal Logic (htl), the graphical system description language of Hybrid Automata, and a proof system for verifying that hybrid automata satisfy their HTL speciications. Th...

Single Electron Tunneling (SET) is an emerging technology which offers greater scaling potential than MOS. The SET technology offers the ability to control the transport of individual electrons. In this paper we investigate the implementation of 7=3 and 7j2 counters in SET technology. Counters are elementary building blocks which can be utilized for the design of larger arithmetic structures, s...

This paper gives the rationale for the Complementary Pass-Transistor Logic (CPL) implementation of threshold gates for the design of complex logic functions. The interesting low-power properties of CPL circuits and the efficiency with which a broad class of functions can be implemented by threshold functions make the proposed methodology extremely useful. A number of implementation examples are...

Diverse advanced logic circuits are fabricated to implement arithmetic functions based on a simple and single molecular beacon platform, including half adder, half subtractor, full adder, full subtractor, and a digital comparator. Dual fluorescence outputs are generated in parallel and a constant threshold value is set to build all the logic circuits. The developed enzyme-free DNA system provid...

Multi-adjoint logic programs generalise monotonic and residuated logic programs [2] in that simultaneous use of several implications in the rules and rather general connectives in the bodies are allowed. As our approach has continuous fixpoint semantics, in this work, a procedural semantics is given for the paradigm of multi-adjoint logic programming and a completeness result is proved. Some ap...