In this work, we present two memristor based chaotic circuits. These circuits are obtained by replacing the nonlinear resistor in the four element Chua’s circuit with a memristor. Hence, these chaotic circuits use only the four basic circuit elements. Moreover, one of these circuits has only one negative element in addition to the nonlinearity. The four element Chua’s circuit requires two negat...

Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which h...

IW circuits are considered quasi3D (2,5D) metal-dielectric circuits. They have a high level of integration circuits, the metal and dielectric losses moderated and the precision of manufacturing for microwave applications [1]-[3]. The architecture of these structures consists in adding to the planar circuits a network of metallic via-hole integrated in the dielectric layer. The via-holes replace...

An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representati...

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are propose...

The Spanish telecommunications regulator recently introduced a capacity-based access system. Under this regulation, entrants pay a flat charge for the interconnection circuits leased to the incumbent operator and are able to freely use these circuits to provide telecommunications services. This paper determines the optimal capacity-based access charge in the presence of time varying demand and ...

Synthesis for Testability has become a major issue as the size and complexity of circuits and systems is rapidly increasing. Due to their good testability design styles based on multiplexors have become very popular. Starting from a function description as a Binary Decision Diagram (BDD) the circuit is generated by a linear time mapping algorithm. Only one additional input and one inverter are ...