Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixedvoltage I/O buffer with 3 × VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design ...

In this paper, a new low-VDD CMOS bandgap reference circuit with small layout area and low power consumption is proposed. The proposed circuit delivering its output voltage below 1V has its Proportional-To-Absolute-Temperature (PTAT) term compensated by the Complementary-proportional-To-AbsoluteTemperature (CTAT) voltage thereby suppressing a change in its output voltage regardless of temperatu...

Contention-less flip-flops (CLFF’s) and separated power supply voltages (VDD) between flip-flops (FF’s) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum op...

The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed Vdd; asymmetric LDD devices exhibit higher Idsat and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower Vdd while higher Idsat is retained. For t...

The novel 2xVDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1xVDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2xVDD tolerant capability. Thus, the new 2xVDD logic gates can be operated under 2xVDD voltage environment without suffering the gate-oxide reliability issue.

Objective: To find out the frequency of vitamin D deficiency (VDD) in healthy children. Study Design: Cross-sectional study. Setting: Department Pediatric Medicine, Sahiwal Teaching Hospital, Sahiwal. Period: July 2022 to December 2022. Material & Methods: A total 80 children either gender aged 6 36 months visiting outpatients department pediatrics during study period adopting convenient sa...

Introduction: Secondary hyperparathyroidism due to vitamin D deficiency (VDD) is thought play a role in glucose homeostasis. The aim of this study was determine the association parathormone and with prediabetes its different cardiovascular risk factors. Methods: This crosssectional conducted among 117 adults newly detected prediabetes. Participants were recruited consecutively from Department E...

This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greaterthan-nominal supply voltage, Vdd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, Vdd,n. In the second, the circuit is power-gated, e...

We propose Crosshairs SRAM to adaptively fix parametric failures and increase yield. It mitigates process variation by tuning VDD and GND of each bitcell inverter independently from its cross-coupled counterpart. It targets failing cells at the intersection of individually-tuned orthogonal VDD and GND rails. We implement 70 32kb test arrays in 45nm CMOS with little modification to a commercial ...

It is essential to control VDD and VTH for low-power, high-speed CMOS design. In this paper, it is shown that these two parameters can be controlled by designers as objectives of design optimization to find better trade-offs between power and speed. Quantitative analysis of trade-offs between power and speed is presented. Some of the popular circuit techniques and design examples to control VDD...