Serum lipids, lipids (cholesterol, triglycerides and phospholipids) and apo-A in d.>1. 063 fraction, HDL2, HDL8 and VHDL of 10 normal subjects and 34 patients with chronic liver diseases (chronic aggressive hepatitis 2A and 2B, and liver cirrhosis in the compensated and decompensated stages) were analyzed. The analysis of d.>1. 063 and its subfractions (HDL2, HDL8 and VHDL) was achieved by rela...

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output ...

In this paper, a tool developed to help in the VHDL design flow of complex systems on silicon is presented. This tool aims to help designers and Project Managers to improve the quality of their VHDL based designs. The tool includes functions oriented towards design management and also functions to analyse the quality of the VHDL descriptions from different points of view. These functions togeth...

This paper presents a model for characterizing delay and power for CMOS logic cells that accounts for input slope and output capacitance loading. A method for deriving the model parameters and VHDL modeling for simple logic gates is presented. The model makes feasible delay and power estimation at VHDL simulation speed, the errors of the model prediction are less than 5% of Spice results.

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be challenge to design high performance low-power systems. Therefore, designers are trying reduce dissipation these systems by using optimization techniques. Different mathematical operations can found the archit...

When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications. The recognized need for formal verification cannot be met by current automatic equivalence and model checking tools, which mainly apply to logic synthesis inputs and outputs, or require manual abstraction....