In transport triggered architectures (TTAs) the programming and operational model is mirrored when compared with regular RISC and VLIW architectures; instead of programming operations which cause data transports as side eeects, in TTAs the transports are programmed, where a transport may trigger an operation if necessary. Transports are therefore visible at the architecture level, and are compl...

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler ...

Digital signal processing (DSP) and multimedia applications are expected to be the dominant workloads on future computer systems. In this paper, we evaluate the performance of a very long instruction word (VLIW) processor using Texas Instruments Inc.’s TMS320C6x and a single-instruction multiple-data (SIMD) processor using Intel’s Pentium II processor (with MMX) on a set of benchmarks. Our benc...

We describe logic and physical synthesis methodology to achieve timing closure on a high-end VLIW/SIMD DSP processor core. The design comprises of approximately 200,000 placeable instances. The target frequency goal was to achieve 250 MHz in 130 nm technology. The VLIW/SIMD DSP is described using TIE (Tensilica Instruction Extension) language, which is a Verilog-like language for description of...

This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machine. A distinctive characteristic of this architecture is the use of register files organized by means of queues, which results in a number of advantages over conventional schemes, but also requires the development of sp...

This paper explores the use of formal verification methods for complex and highly parallel state machines. For this purpose, a framework named Synchronous Transfer Architecture (STA) is being used. STA is a generic framework for digital hardware development that contains VLIW, FPGA, and hardwired ASIC architectures as corner cases. It maintains a strictly deterministic system behavior in order ...

ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical VLIW-based DSP, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilatio...

Processor Martin T. Rowland and Randall A. Helzerman Intel Corporation, Design Technologies 2111 N.E. 25th Avenue JF1-71 Hillsboro, OR 97124-5961 August 23, 1995 Abstract Because dependencies limit the amount of parallelism in an instruction stream, a VLIW or superscalar processor typically cannot execute as many instructions each cycle as it has functional units. This otherwise wasted processi...